1. Technical Field
This invention generally relates to CMOS Integrated Circuit Technology. More specifically, the invention relates to high voltage tolerant CMOS input/output buffer interface circuits.
2. Prior Art
The industry road map for CMOS integrated circuit (IC) technology is to move to lower power supply voltages. There are many reasons for this trend, but the main reasons are the demand for higher integration density and lower power consumption. With the emergence of high performance electronics required for battery operated devices, such as lap-top computers, pagers, cellular phones, etc., it is critical to reduce the size and power consumption of these ICs. Because the industry is also performance driven, ultra fast CMOS devices have very thin gate oxides that determine the maximum voltage these devices can withstand without causing permanent damage to the device.
Each new technology release may yield higher chip density with faster clock speeds and lower power consumption. This may substantially improve performance and significantly reduce the product cost. This creates a problem, however, when signals are driven on and off the chip through older or xe2x80x9cstandards interfaces. New interface standards are being developed to take advantage of the newer technologies, however many older (higher voltage) interfaces remain in use. One of the challenges in I/O design today is to design I/O buffers that meet the older specifications for high voltage swings. If a standard 5 volt signal were applied directly to a CMOS I/O processed in a state-of-the-art technology (i.e., 1.5V CMOS technology), the stress caused by the 5 volt signal would cause permanent damage to the silicon IC.
An object of this invention is to provide an improved high voltage tolerant input/output buffer circuit.
Another object of the present invention is to use an integrated circuit process feature and circuit design techniques to meet the high voltage interface specifications without causing damage to the silicon.
These and other objectives are achieved with a high voltage tolerant CMOS input/output interface circuit. In this circuit, a process feature called xe2x80x9cdual-gatexe2x80x9d or xe2x80x9cthick-oxidexe2x80x9d process is used on any devices that will be exposed to high voltage. The thick-oxide devices have a larger capacitance and lower bandwidth, and therefore, preferably, they are only used where exposure to high voltage can cause damage. The remaining devices on the interface circuit may all use the standard process with the thinner oxide, allowing the I/O and the core IC to run at maximum speed. The circuit design topology also limits the number of devices that are exposed to high voltage. Preferably, the protection scheme is broken down into two parts: the driver and receiver.
Further benefits and advantages of the invention will become apparent from a consideration of the following detailed description, given with reference to the accompanying drawings, which specify and show preferred embodiments of the invention.